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Through-silicon via (TSV) is finding increasing use in microelectronics. By offering higher numbers of  IOs, shorter signal paths, hermetic sealing, better impedance control and smaller footprints, the technology meets many semiconductor and MEMS industry demands. Besides being thermally strong, XiVIA also saves costs thanks to its tremendous yield and good compatibility with other processing. Plating time is typically 10–100 times shorter than regular manufacturing, for example. XiVIA opens up many 2D and 3D SysteminPackage (SiP) opportunities for the space and interposer industry. It has already been successfully applied for manufacturing fine-pitch  component interposers. This interposer features electrical TSVs through both silicon substrate and interposer, Flip-Chip-mounted bare dies, passive components mounted as SMD, and soldered wafer-to-wafer interconnections.

The Ã…AC Microtec interposer with XiVIAâ„¢ TSV adapts the complex substrate to the standard footprint by re-routing on the interposer.

XiVIA process advantages

The XiVIA method has several key advantages. The metal in the via is formed together with the conductor layer, rather than in two different steps, and wafer thinning is avoided, which facilitates handling. A novel constriction inside the via increases yield during metal deposition, decreases copper plating time, and adds mechanical strength. Furthermore, current equipment can be used.

Passes tough space testing requirements

The XiVIA design is extremely robust and the process sequence has shown high yield numbers. Extensive mechanical, electrical and thermal evaluations performed on a large set of vias produced in this way demonstrate
compliance with stringent space demands, e.g. the vibration spectrum for the ESA/ Ariane 5 launcher. All vias in the tested set passed 3σ analysis.ÅAC XiVIA® is compatible with today's MEMS foundry equipment and easy to implement. If you need a low resistive, robust, and cost efficient through silicon via, contact us today for a license discussion.

ÅAC XiVIA® through silicon via (TSV) Summary:

• Support robust silicon interposer (via-first)
• Metallic < 10 mΩ
• Via metalization and redistribution layer at the same time
• Stable process with today's equipment
• Process licensed to Silex Microsystems
• Short plating time on plugged vias
• Fatigue pull test for 17000 cycles at 4 Mpa - passed
• Pull strength > 20 MPa - passed
• Shear strength > 30 MPa - passed
• Thermal shock to -160°C - passed
• Thermal cycling, -40°C to +125°C for 500 cycles - passed
• Down to 100 µm pitch

Download Interposer and XiVIA® data sheet (PDF) and a presentation XiVIA in space

XiVIA® is excellent for robust silicon interposers.